1. Technical Field
The present disclosure relates to a ring oscillator.
2. Description of the Related Art
A Time-to-Digital Converter circuit or TDC is substantially a circuit that measures a time period and converts it into a digital number.
The time period considered can be a period of time between a start signal and a stop signal, as for example those shown in FIG. 1. Alternatively, it is possible to consider for example the activation period of a digital signal.
Time-to-Digital converter circuits are used in several circuits, such as for example:                circuits for the digital pulse width modulation or PWM, wherein the information is coded in the form of duration in time of each pulse;        circuits for the determination of the distortion of the harmonics in a signal as THD (acronym of Total Harmonic Distortion), for example in a transmission channel;        analog-to-digital ramp converter circuits or Ramp ADCs;        circuits for the driving of bridges with digital signals, wherein it is necessary to execute a conversion of a digital signal supplied at the input in a time period;        
and other similar circuits.
During the last years different solutions have been developed and proposed, suitable for improving the performances of these converters.
One solution is shown for example in FIG. 2 and provides the use of a counter that counts how many pulses of a clock signal CLK are received between a start signal Start and a stop signal Stop. In some cases, the start signal can be the same pulse signal CLK.
This solution, although simple and advantageous, however has some drawbacks. In fact, the time periods that can be measured are long or short but must necessarily be greater than the pulse of the pulse signal CLK, that, up to date, is in the order of the tens of nanoseconds. This converter circuit A/D thus has a very low resolution.
A second solution that tries to overcome this drawback is shown in FIG. 3. In this case, the converter circuit proposed comprises a plurality of Flip-Flops being connected in cascade to each other and having respective output terminals connected to a logic circuit LOG. In particular, each Flip-Flop substantially receives two input signals: a cyclic or clock CLK signal and a State signal. The clock signal CLK is supplied by a detector through a first logic gate and propagated from a Flip-Flop to the other by means of the interposition of a plurality of inverters in cascade. The detector also supplies through a second input logic gate the State signal to an input terminal of each Flip-Flop, that receives it with a predetermined delay dues to the offset timing realized by the clock signal CLK delayed by the plurality of inverters.
The logic circuit LOG, at the arrival of the stop signal Stop, tests the status of the Flip-Flops, in particular the signals present on the output terminals connected thereto, and on the basis of this status, by means of suitable processing, supplies the digital value corresponding to the activation time period of the converter, i.e., of the time elapsed between the Start and Stop signals.
The converter just described thus measures the time period by means of Flip-Flops and thus the speed of the counter is substantially defined by the speed of these logic elements that, at present, is in the order of 100 ps. Moreover, for measuring long time periods it is necessary to increase the number of the Flip-Flops in cascade.
This second solution, although advantageous and with a good resolution, is thus convenient only for the conversion of short time periods, with a reduced number of Flip-Flops to be used, while it is little attractive for the conversion of long time periods due to the increase of the integration area requested as well as to the corresponding high consumption in terms of power.
A third solution is shown in FIG. 4. This solution provides to use a phase-locked circuit or PLL (acronym of “Phase-Locked Loop”) or a DLL circuit (acronym of “Delay Locked Loop”) able to generate a signal with a same frequency as that of an external reference clock signal CLK and whose phase has a fixed relation with that of this reference signal. A converter of this type essentially comprises a counter, which allows to count the loops of the clock signal in the ring of the PLL/DLL circuit between a start signal and a stop signal, this number of loops being the integer part of the value of the time period elapsed between the Start and Stop signals. The converter also comprises a logic LOG that allows to determine, according to the position of the clock signal inside the circuit itself, a fractional part of the value of this time period.
This solution, although accurate and attractive with respect to the previous ones, shows a high complexity. In fact, the PLL/DLL circuit is rather complex to be realized and requires a rather big integration area.
A further solution suitable for solving these drawbacks is shown in FIG. 5. The converter circuit is in this case realized by means of a ring oscillator made of an odd number of inverters placed in cascade and crossed by a clock signal. A counter connected to this ring oscillator counts the loops of the clock signal in the time period between a start signal Start and a stop signal Stop. Finally, an Arithmetic Logic Unit ALU, connected to the counter and to the ring oscillator, with suitable mathematic operations determines a value corresponding to the duration of the time period elapsed between these signals. This value comprises an integer part determined by the number of loops counted by the counter by the number of inverters of the ring oscillator and a fractional part determined according to the detection of the active inverter at the arrival of the stop signal Stop.
The substitution of the circuit DLL/PLL with the ring oscillator remarkably simplifies the realization of the analog part of the converter circuit and remarkably reduces the integration area required. However, the ring oscillator requires for its operation a necessarily odd number of inverters which exacerbates and makes it more complex at the circuit level the logic arithmetic unit to be used in couple with this ring oscillator.